1. Field of the Invention
This disclosure is directed to a method of forming a gate pattern and a semiconductor device having the gate pattern. This disclosure is particularly directed to a method of forming a staggered gate pattern and a semiconductor device having the gate pattern.
2. Description of the Related Art
In order to maximize the density of a semiconductor device, in particular the density of a gate, it is often required to form a staggered gate pattern. For example, this gate pattern includes a plurality of gate bars parallel to each other in a first direction, and each gate bar is broken up by gaps. Moreover, the gaps are located in a plurality of stripe zones parallel to each other in a second direction which is substantially perpendicular to the first direction, but the gaps in each stripe zone are not continuous, that is, there are gaps adjacent to each other across gate bars in each stripe zone.
In current semiconductor manufacturing processes, in order to form a staggered gate pattern, a double patterning technique is employed widely.
FIGS. 1A to 1B show trimming slots formed in a conventional double patterning technique and a gate pattern obtained by using the trimming slots. Referring to FIG. 1A, a mask having the trimming slots is disposed above a plurality of gate bars parallel to each other obtained after line etching. The positions of the trimming slots correspond to the positions of the gaps breaking up the gate bars. The positions of the trimming slots are staggered because a staggered gate pattern is to be formed. Next, referring to FIG. 1B, a staggered gate pattern is formed after trimming slot etching is performed on the gate bars.
FIGS. 2A to 2D specifically show a method of forming a staggered gate pattern by employing a conventional double patterning technique.
First, as shown in FIG. 2A, a resist pattern 210 having a plurality of openings is formed by a first photolithography process, the plurality of openings being parallel to each other and extending continuously. Next, as shown in FIG. 2B, a first etching process is performed by using the resist pattern 210 as a mask so as to form a plurality of gate material bars 260 on a substrate 250, the plurality of gate material bars 260 being parallel to each other and extending continuously. Then, as shown in FIG. 2C, a resist pattern 220 having trimming slots is formed by a second photolithography process. Finally, as shown in FIG. 2D, a second etching process is performed by using the resist pattern 220 as a mask so as to form staggered gaps in the gate material bars 260 on the substrate 250, thereby forming the staggered gate pattern.
FIGS. 3A to 3E specifically show another method of forming a staggered gate pattern by employing a conventional double patterning technique. This method additionally forms a hard mask layer on a gate material layer. After forming a staggered hard mask pattern by using a similar method, the hard mask pattern is transferred to the underlying gate material layer, thereby forming a staggered gate pattern.
First, as shown in FIG. 3A, a resist pattern 310 having a plurality of openings is formed by a first photolithography process, the plurality of openings being parallel to each other and extending continuously. Next, as shown in FIG. 3B, a first etching process is performed by using a resist pattern 310 as a mask so as to form a plurality of hard mask bars 370 on the gate material layer 360 on a substrate 350, the plurality of hard mask bars 370 being parallel to each other and extending continuously. Then, as shown in FIG. 3C, a resist pattern 320 having trimming slots is formed by a second photolithography process. Next, as shown in FIG. 3D, a second etching process is performed by using the resist pattern 320 as a mask so as to form staggered gaps in the hard mask bars 370 on the gate material layer 360 on the substrate 350, thereby forming a staggered hard mask pattern. Finally, as shown in FIG. 3E, a third etching process is performed by using the hard mask pattern as a mask so as to form the staggered gate pattern.
After forming the gate pattern (e.g., a polysilicon gate pattern) by using any one of the above methods, the material of the gate may be further replaced by a metal, thereby forming a staggered metal gate pattern.
The present inventors have conducted in-depth investigation on the above method of forming a staggered gate pattern, and have found that the following problems exist.
First, in deep submicron field, strict control is needed for the size of trimming slots, especially the longitudinal size H1 of trimming slots (referring to FIGS. 2C and 3C, which corresponds to the length of the gaps breaking up the gate bars), which makes the photolithography process window of trimming slots very small.
Second, in deep submicron field, corners of obtained trimming slots are rounded significantly due to the margin of trimming slot photolithography, i.e., the obtained trimming slots are not in desired rectangular shape (referring to FIG. 1A). Moreover, after trimming slot etching, corners of an obtained gate are sharp correspondingly rather than being desired right angles (referring to FIG. 1B). Thus, the shape and size of a gate pattern can not be precisely controlled, thereby causing an adverse effect on the performances of a semiconductor device. Further, if a metal gate structure is to be employed, the sharp corners of the gate make metal filling difficult when replacing the material of the gate with the metal, which also causes an adverse effect on the performances of the semiconductor device.